1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to the control of instruction issue within superscalar data processing systems.
2. Description of the Prior Art
It is known to provide superscalar data processing systems including multiple instruction pipelines so that multiple streams of program instructions can be executed in parallel thereby increasing processor throughput. A problem with such systems is that data dependencies between program instructions can require that an output of one instruction is used as an input to another instruction such that, if those two instructions are issued together, then the true input to the younger instruction will not be available when required since it will not yet have been calculated by the older instruction. In order to deal with this situation it is known to provide data dependency hazard checking mechanisms which are responsive to the source and destination register specifiers of program instructions to be issued to identify any combinations of instructions with a data dependency that would cause an error if those instructions were issued together. If such a data hazard is detected, then the younger instruction(s) can be held back and issued in a later cycle such that the data hazard will not arise. This reduces processing performance since the parallel execution capabilities are not fully used.